As is known, the expression "emitter switching" is generally used to denote a circuit configuration wherein a first bipolar or MOS transistor, operated at a low voltage, cuts off the flow of current to an emitter terminal of a second bipolar transistor operated at a high voltage, for example, thereby turning it off.
To illustrate the point, reference will be made to FIGS. 1 and 2, which show a monolithic integrated device in an emitter switching configuration of the MOS-bipolar type and its electric diagram, respectively.
More particularly, FIG. 1 is a detail view of a monolithic integrated device of the emitter switching type, carrying the reference numeral 20, which is formed in a semiconductor material substrate 1 having a first conductivity type, specifically N++.
Also with reference to FIG. 1, the device 20 includes a first epitaxial layer 2 formed on the substrate 1 and having the same conductivity type of the substrate, specifically N-.
The device 20 further includes a first transistor T1 of the bipolar type and a second transistor M1 of the MOS type which are connected together through respective emitter E and drain D terminals, as shown in FIG. 2.
As shown in FIG. 2, the first transistor T1 is of the NPN type and the second transistor M1 is of the N-MOS type.
With further reference to FIG. 1, the first transistor T1 has a collector region 1, 2 formed in the first epitaxial layer 2 of the substrate 1, and a base region 3, 4, 5 having a second conductivity type, specifically P, including a first buried region 3 formed in the first epitaxial layer 2, and a first diffused region 4 which extends from the first buried region 3 to contact a top surface of the integrated device 20 through a first surface contact region 5 having a high concentration of a dopant material, specifically of the P+ type.
The region 5 is arranged to minimize the contact resistance to the top surface of the device.
The first transistor T1 further comprises an emitter region 6, 7 with the first conductivity type, specifically N, which is bounded by the base region 3, 4, 5 and includes a second buried region 6 formed over the first buried region 3, and a second diffused region 7 having a high concentration of a dopant material, specifically of the N+ type, and extending from the second buried region 6 to contact the top surface of the integrated device 20.
Referring further to FIG. 1, the second transistor M1 has a drain region 6, 7 included in the emitter region 6, 7 of the first transistor T1.
Said second transistor M1 also has a second epitaxial layer 8 located above the second buried region 6 and having the first conductivity type, specifically the N- type.
The epitaxial layer 8 includes, at the top surface of the device 20, an enhancement region 11 of the N-well type having conductivity of the N+ type.
During the device 20 integration process, when the first surface contact region 5 is formed, a "deep body" region 5' is also formed within the epitaxial layer 8 which includes a "body" region 9 in its upper portion, both regions being parts of the second transistor M1, as shown in FIG. 1.
The regions 5' and 9 have the second, respectively P+ and P, conductivity type.
Connected with the region 9 is also a third diffused region 10 having a high concentration of dopant material and the first conductivity type, specifically N+, and including a source region of the second transistor M1.
Referring now to FIGS. 3 and 4, there are shown a monolithic integrated device 20A in the emitter switching configuration of the bipolar-bipolar type and its electric diagram, respectively.
This second known embodiment of an emitter switching device has the second transistor M1 of the MOS type replaced by a second (NPN) transistor T2 of the bipolar type which is connected with a respective collector terminal C to the emitter terminal E of the first transistor T1, as shown in FIG. 4.
With reference to FIG. 3, the second transistor T2 has a collector region 6A, 7A included in the emitter region 6A, 7A of the first transistor T1.
Said second transistor T2 also has a second epitaxial layer 8A, located above the second buried region 6A and having the first conductivity type, specifically N-.
The second epitaxial layer 8A includes, at the top surface of the device 20A, an enhancement region 11A of the N-well type which has conductivity of the N+ type.
The second transistor T2 further comprises a base region 5A', formed in the second epitaxial layer 8A, which contacts the top surface of the integrated device 20A through a second surface contact region 5" at a high concentration of a dopant material, specifically of the P+ type, as shown in FIG. 3.
Further with reference to FIG. 3, formed in the base region 5A', 5A" is a third diffused region 10A at a high dopant concentration, having the first conductivity type, specifically N+, and including an emitter region of the second transistor T2.
To illustrate the problem pertinent to this invention, reference should be made to FIG. 5, which shows a complete electric diagram of a monolithic integrated device in the emitter switching configuration of the MOS-bipolar type.
As shown in FIG. 5, a device driving voltage Vgs is applied between a gate terminal G and a source terminal S of the second transistor M1.
The current required by the specific application is supplied by a supply voltage Vbb being applied to the base terminal B of the first transistor T1.
Connected to the collector terminal C of the first transistor T1 is a generic load L, and connected to the base terminal B is a power-down diode D of the Zener type.
During the device power-on phase, the first transistor T1 begins to conduct upon a given threshold value Vs being exceeded by the voltage Vg presented at the gate terminal of the second transistor M1, which results in the transistor M1 itself becoming conductive.
During this phase, the diode D is in the `off` state because its Zener voltage Vz is selected from the designing stage to have a higher value than that of the voltage Vbe present across the base B and emitter E terminals of the first transistor T1.
During the power-down phase, that is as the voltage Vg drops to a value below the threshold voltage Vs, the second transistor M1 is turned off, and the current presented at the emitter terminal E of the first transistor T1 is cancelled.
During this phase, the current presented at the collector terminal C cannot flow through the base region 3A, 4A, 5A.
Therefore this current will flow to a ground terminal through the diode D, whose Zener voltage Vz, although required to be higher than the voltage Vbe, is to be the lowest possible in order to reduce dissipation.
During the device power-down, the emitter/drain voltage Ve/d attains a value equal to the sum of the reverse breakdown voltage of the emitter/base junction, BVebo, of the bipolar component plus the Zener voltage Vz relating to the value of the current presented at the collector terminal C.
If the voltage Ve/d exceeds the value of the breakdown voltage BVdss of the second transistor M1, then the device may be destroyed.
Thus, the operation of the emitter switching device during the power-down step is determined by the following condition being met: EQU BVebo+Vz&lt;BVdss 1]
The relation 1] represents a characteristic condition of the device, and accordingly, there is a tendency from the designing stage to minimize the sum of the two terms on the left side of the inequality relative to the value of BVdss.
The voltage Vz is dictated by the diode D, but its value cannot be selected smaller than the voltage Vbe, for the reasons set forth hereinabove.
In principle, the diode D could be replaced with at least two or more diodes in series, placed in forward conduction to the ground terminal and having an equivalent threshold voltage above the voltage Vbe of the transistor T1.
In any case, the value of the Zener voltage Vz cannot be less than a few volts in actual practice.
The value of the voltage BVebo is dependent on the doping of the base 3A, 4A, 5A and emitter 6A, 7A regions that form the base-emitter junction of the first transistor T1.
The breakdown voltage of this junction cannot be a low value, e.g., equal to the Zener diode voltage Vz. That is because, as explained hereinafter, the doping level required for the base region 3A, 4A, 5A and the emitter region 6A, 7A, respectively, would then interfere with proper operation of the emitter switching device.
A first known approach to lowering the value of the breakdown voltage of the base-emitter junction, BVebo, of the first transistor T1 was to minimize the resistivity of the base region 3A, 4A, 5A, while improving the device power-down performance, when the current at the collector terminal C is directed to the ground terminal.
However, the resistivity of the base region 3A, 4A, 5A cannot be decreased at will because, additionally to reducing the gain of the first transistor T1, the P-type dopant (boron) that defines this region--due to its higher diffusion rate than the N-type dopant (antimony) that defines the emitter region 6A, 7A--tends to compensate for, and hence to make highly resistive, the N region underlying the second transistor M1, as illustrated by the graph in FIG. 6.
This involves an undesired high Ron of the second transistor M1, which tends to restrict the flow of current through the device, as illustrated by the graphs in FIG. 7.
In order to limit the increase in Ron of the second transistor M1, resulting from a heavily doped base region, there are two actions to be taken.
A first action is to enhance the antimony-doped emitter region 6A, 7A, before forming the second epitaxial layer 8A, by the use of an N-type dopant having a higher diffusion coefficient, such as phosphorus, so as to utilize the back-diffusion of the dopant toward the surface tending to enhance the region underlying the second transistor M1 and, hence, to compensate for the boron from the base region 3A, 4A, 5A.
While being in many ways advantageous, this first action has a disadvantage in that the phosphorus would also diffuse toward the base region 3A, 4A, 5A, causing a substantial increase in resistivity.
Therefore, this action tends, albeit in an indirect manner, to simultaneously favor the power-down condition 1] and adversely affect the dynamic performance of the device, as illustrated by the graphs in FIG. 8.
The second action is to reduce the thickness of the second epitaxial layer 8A such that the pattern of the phosphorus dopant defining the enhancement region 11A of N-well will overlap the emitter region 6A, 7A, thereby compensating for the boron from the base region 3A, 4A, 5A.
While achieving its objective, not even this second action is devoid of drawbacks.
In fact, while requiring no enhancement of additional dopant on the emitter terminal E, as the first action did, and leaving the resistivity unaltered of the base region 3A, 4A, 5A, this action brings about a substantial decrease in the breakdown voltage BVdss of the second transistor M1, contrary to the device power-down condition expressed by relation 1], as illustrated by the graphs in FIG. 9.
A third action would be that of bringing the emitter region 6A, 7A closer to the first diffused region 4A such that the pattern of N-type dopant defining the emitter region 6A, 7A overlaps a base region where the dopant pattern has a higher charge concentration than the base first buried region 3A.
Not even this third action can provide a lower value of BVebo than 30V, although it would indeed bring down the breakdown voltage BVebo between the base terminal B and the emitter terminal E by no less than about 30V, and this without altering the electric parameters of the second transistor M1.
In the instance of an emitter switching device of the bipolar-bipolar type, the condition for power-down and the problems brought forth in discussing conventional approaches to an emitter switching device of the MOS-bipolar type apply again, once BVdss and Ron of the MOS component are substituted with BVces and the collector resistance, respectively, of the low-voltage bipolar component.